Advance Program at a glance

Thursday October 16th:
  09:00 - 09:45 Registration
  09:45 - 10:00 Welcome
  10:00 - 11:00 Session Uniprocessor Scheduling 1
  11:00 - 11:30 Break
  11:30 - 12:30 Session Dependable Real-Time Systems
  12:30 - 14:00 Lunch
  14:00 - 15:30 Invited Talk on Highly Scalable Aggregate Computations in Cyber-Physical Systems
  15:30 - 16:00 Break
  16:00 - 17:30 Session Pattern-Triggered Task Scheduling

  Social Event: All participants are invited to a banquet in Rennes downtown.
  During this banquet, the 'Best Student Paper' of RTNS 2008 will be awarded.


Friday October 17th:
  09:00 - 10:30 Session Uniprocessor Scheduling 2
  10:30 - 11:00 Break
  11:00 - 12:30 Session Distributed and Multiprocessor Scheduling
  12:30 - 14:00 Lunch 
  14:00 - 15:00 Session Worst Case Execution Time Estimation
  15:00 - 16:30 Junior Workshop Presentations
  16:30 - 16:45 Break
  16:45 - 17:15 Junior Workshop Posters



Accepted papers

Session 1: Uniprocessor scheduling 1

An Investigation into Server Parameter Selection for Hierarchical Fixed Priority Pre-emptive Systems

Robert Davis, University of York
Alan Burns, University of York


User Land Approximate Slack Stealer with Low Time Complexity

Damien Masson, Laboratoire d'informatique de l'institut Gaspard-Monge, Université Paris-Est
Serge Midonnet, Laboratoire d'informatique de l'institut Gaspard-Monge, Université Paris-Est



Session 2: Dependable real-time systems

Enhancing a Dependable Multiserver Operating System with Temporal Protection via Resource Reservations

Antonio Mancina, Scuola Superiore Sant'Anna
Jorrit Herder, Vrije Universiteit Amsterdam
Ben Gras, Vrije Universiteit Amsterdam
Andrew Tanenbaum, Vrije Universiteit Amsterdam


Towards a Unified X-by-Wire Solution with HUMS, HM & TTP: Lessons Learned in Implementing it to a Drive-by-Wire Vehicle

John Melentis, University of Sussex
Elias Stipidis, University of Sussex
Periklis Charchalakis, University of Sussex
Falah Ali, University of Sussex



Session 3: Pattern-triggered task scheduling

(m,k)-Firm Constraints and DBP Scheduling: Impact of the Initial k-Sequence and Exact Feasibility Test

Joel Goossens, Universite Libre de Bruxelles


Exact Scheduling Analysis of Non-Accummulatively Monotonic Multiframe Tasks

Areej Zuhily, University of York
Alan Burns, University of York


Event-Pattern Triggered Real-Time Tasks

Jan Carlson, Mälardalen Real-Time Research Centre (MRTC)
Jukka Mäki-Turja, Mälardalen Real-Time Research Centre (MRTC)
Mikael Nolin, Mälardalen Real-Time Research Centre (MRTC)



Session 4: Uniprocessor scheduling 2

Quantifying the Sub-Optimality of Uniprocessor Fixed-Priority Scheduling

Sanjoy Baruah, University of North Carolina
Alan Burns, University of York


Improved Approximate Response Time Bounds for Static-Priority Tasks

Thi Huyen Chau Nguyen, Lisi/Ensma
Pascal Richard, Lisi/Ensma
Enrico Bini, Scuola Superiore Sant'Anna


Feasibility Analysis of Non-Concrete Real-Time Transactions With EDF Assignment Priority

Ahmed Rahni, LISI/ENSMA
Emmanuel Grolleau, LISI/ENSMA
Michael Richard, LISI/ENSMA



Session 5: Distributed and multiprocessor scheduling

Minimizing the Number of Processors Used by Real-Time Distributed Systems

François Dorin, LISI - Laboratoire d'Informatique Scientifique et Industrielle
Michael Richard, LISI - Laboratoire d'Informatique Scientifique et Industrielle
Emmanuel Grolleau, LISI - Laboratoire d'Informatique Scientifique et Industrielle
Pascal Richard, LISI - Laboratoire d'Informatique Scientifique et Industrielle


Pfair Scheduling Improvement to Reduce Interprocessor Migrations

Dalia Aoun, Université de Nantes - IRCCyN
Anne-Marie Deplanche, Université de Nantes - IRCCyN
Yvon Trinquet, Université de Nantes - IRCCyN


Delay Evaluation and Compensation in Ethernet-Networked Control Systems

Boussad Addad, LURPA, ENS-Cachan
Said Amari, LURPA, ENS-Cachan



Session 6: Worst-case execution time estimation

Attacking the Sources of Unpredictability in the Instruction Cache Behavior

Enrico Mezzetti, University of Padua
Niklas Holsti, Tidorum Ltd.
Antoine Colin, Rapita Systems Ltd.
Guillem Bernat, Rapita Systems Ltd.
T. Vardanega, University of Padua


Accurate Analysis of Memory Latencies for WCET Estimation

Roman Bourgade, IRIT - University of Toulouse
Clément Ballabriga, IRIT - University of Toulouse
Hugues Cassé, IRIT - University of Toulouse
Christine Rochange, IRIT - University of Toulouse